Communication Power Optimization for Network-on-Chip Architectures

Network-on-Chip (NoC) architecture is emerging as a practical interconnection architecture for future systems-on-chip products. In this paper, an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links is proposed. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including network topology, task assignment, tile mapping, routing path allocation, task scheduling, and link speed assignment. The experimental results demonstrate that the proposed design technique can reduce energy consumption by an average of 28% over existing techniques.